adapter/spi_via_usi_driver.c

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// This file has been prepared for Doxygen automatic documentation generation.
#include <avr/io.h>
#include <avr/interrupt.h>


/* USI port and pin definitions.
 */
#define USI_OUT_REG PORTB //!< USI port output register.
#define USI_IN_REG  PINE  //!< USI port input register.
#define USI_DIR_REG DDRB  //!< USI port direction register.
#define USI_CLOCK_PIN PB2 //!< USI clock I/O pin.
#define USI_DATAIN_PIN  PB1 //!< USI data input pin.
#define USI_DATAOUT_PIN PB0 //!< USI data output pin.




/*  Speed configuration:
 *  Bits per second = CPUSPEED / PRESCALER / (COMPAREVALUE+1) / 2.
 *  Maximum = CPUSPEED / 64.
 */
#define TC0_PRESCALER_VALUE 256 //!< Must be 1, 8, 64, 256 or 1024.
#define TC0_COMPARE_VALUE   1 //!< Must be 0 to 255. Minimum 31 with prescaler CLK/1.




/*  Prescaler value converted to bit settings.
 */
#if TC0_PRESCALER_VALUE == 1
  #define TC0_PS_SETTING (1<<CS00)
#elif TC0_PRESCALER_VALUE == 8
  #define TC0_PS_SETTING (1<<CS01)
#elif TC0_PRESCALER_VALUE == 64
  #define TC0_PS_SETTING (1<<CS01)|(1<<CS00)
#elif TC0_PRESCALER_VALUE == 256
  #define TC0_PS_SETTING (1<<CS02)
#elif TC0_PRESCALER_VALUE == 1024
  #define TC0_PS_SETTING (1<<CS02)|(1<<CS00)
#else
  #error Invalid T/C0 prescaler setting.
#endif



unsigned char storedUSIDR;



struct usidriverStatus_t {
  unsigned char masterMode : 1;       
  unsigned char transferComplete : 1; 
  unsigned char writeCollision : 1;   
};

volatile struct usidriverStatus_t spiX_status; 



#if 0
ISR(SIG_OUTPUT_COMPARE1A)
{
  USICR |= (1<<USITC);  // Toggle clock output pin.
}
#endif //#if 0


ISR(SIG_USI_OVERFLOW)
{
  // Master must now disable the compare match interrupt
  // to prevent more USI counter clocks.
  if( spiX_status.masterMode == 1 ) {
    TIMSK &= ~(1<<OCIE0A);
  }

  // Update flags and clear USI counter
  USISR = (1<<USIOIF);
  spiX_status.transferComplete = 1;

  // Copy USIDR to buffer to prevent overwrite on next transfer.
  storedUSIDR = USIDR;
}



void spiX_initmaster( char spi_mode )
{
  // Configure port directions.
  USI_DIR_REG |= (1<<USI_DATAOUT_PIN) | (1<<USI_CLOCK_PIN); // Outputs.
  USI_DIR_REG &= ~(1<<USI_DATAIN_PIN);                      // Inputs.
  USI_OUT_REG |= (1<<USI_DATAIN_PIN);                       // Pull-ups.

  // Configure USI to 3-wire master mode with overflow interrupt.
  USICR = (1<<USIOIE) | (1<<USIWM0) |
          (1<<USICS1) | (spi_mode<<USICS0) |
          (1<<USICLK);

  // Enable 'Clear Timer on Compare match' and init prescaler.
  TCCR0A = TC0_PS_SETTING;

  //TCCR0A = (1<<WGM01);

  // Init Output Compare Register.
  OCR0A = TC0_COMPARE_VALUE;

  // Init driver status register.
  spiX_status.masterMode       = 1;
  spiX_status.transferComplete = 0;
  spiX_status.writeCollision   = 0;

  storedUSIDR = 0;
}



void spiX_initslave( char spi_mode )
{
  // Configure port directions.
  USI_DIR_REG |= (1<<USI_DATAOUT_PIN);                      // Outputs.
  USI_DIR_REG &= ~(1<<USI_DATAIN_PIN) | (1<<USI_CLOCK_PIN); // Inputs.
  USI_OUT_REG |= (1<<USI_DATAIN_PIN) | (1<<USI_CLOCK_PIN);  // Pull-ups.

  // Configure USI to 3-wire slave mode with overflow interrupt.
  USICR = (1<<USIOIE) | (1<<USIWM0) |
          (1<<USICS1) | (spi_mode<<USICS0);

  // Init driver status register.
  spiX_status.masterMode       = 0;
  spiX_status.transferComplete = 0;
  spiX_status.writeCollision   = 0;

  storedUSIDR = 0;
}



char spiX_put( unsigned char val )
{
  // Check if transmission in progress,
  // i.e. USI counter unequal to zero.
  if( (USISR & 0x0F) != 0 ) {
    // Indicate write collision and return.
    spiX_status.writeCollision = 1;
    return 1;
  }

  // Reinit flags.
  spiX_status.transferComplete = 0;
  spiX_status.writeCollision = 0;

  // Put data in USI data register.
  USIDR = val;

  // Master should now enable compare match interrupts.
  if( spiX_status.masterMode == 1 ) {
    TIFR |= (1<<OCF0A);   // Clear compare match flag.
    TIMSK |= (1<<OCIE0A); // Enable compare match interrupt.
  }

  if( spiX_status.writeCollision == 0 ) return 1;
  return 0;
}



unsigned char spiX_get(void)
{
  return storedUSIDR;
}



void spiX_wait(void)
{
  do {} while( spiX_status.transferComplete == 0 );
}



// end of file

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